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Title: Multi-channel integrated circuit

Abstract: A multi-channel integrated circuit is provided in which each channel has an analog section and a digital section. Each channel of the readout chip employs low noise charge sensitive amplifier at its input followed by other circuitry such as shaper, pole-zero, peak hold, different comparators, buffers and digital control and readout. Each channel produces a self-trigger and a fast timing output. Channel-to-channel time differences are also recorded. Integrated circuit also provides a large dynamic range to facilitate large range of applications. The trigger threshold can be adjusted to provide energy discrimination. The chip has different, externally selectable, operational modes including a sparse readout mode in which only the channels which have received signals greater than a preselected threshold value are read out. The sparse readout mode results in increased data throughput, thus providing fast data acquisition capabilities.

Patent Number: 7,417,472 Issued on 08/26/2008 to Tumer,   et al.

Inventors: Tumer; Tumay O. (Riverside, CA), Visser; Gerard (Bloomington, IN)
Assignee: Nova R&D, Inc. (Riverside, CA)
Appl. No.: 11/521,430
Filed: September 15, 2006
Related U.S. Patent Documents
Application NumberFiling DatePatent NumberIssue Date
10779730Feb., 20047126386
10279004Oct., 20026720812
60330596Oct., 2001

Current U.S. Class: 327/70 ; 327/51; 327/69
Current International Class: H03B 17/00 (20060101); G06F 11/00 (20060101)
Field of Search: 327/170,51,69-71,58,18,80,94,77,90 378/98.11,98.9

References Cited [Referenced By]
U.S. Patent Documents
3430197 February 1969 Brown
3740760 June 1973 Johnson et al.
3863056 January 1975 Klein
3900744 August 1975 Lammers
4131798 December 1978 Reddy et al.
4556982 December 1985 Dunn
4857737 August 1989 Kamae et al.
5696458 December 1997 Tumer et al.
5757794 May 1998 Young
5943388 August 1999 Tumer
6150849 November 2000 Tumer
6333648 December 2001 Tumer
6657200 December 2003 Nygard et al.
6720812 April 2004 Tumer
7126386 October 2006 Tumer et al.

Other References

Kravis, Scott D., et al., "Test Results of the Readout Electronics for Nuclear Applications (RENA) Chip Developed for Position-Sensitive Solid State Detectors," SPIE (Society of Photo-Optical Instrumentation Engineers), vol. 3445, Jul. 1998, pp. 374-382. cited by other .
Kravis, Scott D., et. al., "A multichannel readout electronics for nuclear application RENA) chip developed for position sensitive solid state detectors," Nuclear Instruments & Methods in Physics Research, A 422, 1999, pp. 352-356. cited by other.

Primary Examiner: Le; Dinh T.
Attorney, Agent or Firm: Fish & Associates, PC
Parent Case Text


This application is a continuation of U.S. patent application Ser. No. 10/779,730 filed Feb. 18, 2004 now U.S. Pat. No. 7,126,386, issued as US Patent which was a continuation of U.S. patent application Ser. No. 10/279,004 Oct. 24, 2002, issued as U.S. Pat. No. 6,720,812 which was a continuation-in-part application of provisional application Ser. No. 60/330,596 filed Oct. 25, 2001. The entire disclosure of those related applications are incorporated herein by reference for all purposes.
Claims


What is claimed is:

1. An integrated circuit comprising at least one register and at least one channel comprising at least one input, wherein at least one signal is received by said at least one input, and wherein said at least one channel comprises: at least one amplifier with at least one feedback circuit connected to said at least one input and amplifies said at least one signal, wherein said at least one feedback circuit has at least one capacitance and at least one resistance; at least one processing circuit connected to said at least one amplifier to process said at least one signal; at least one trigger circuit connected to said at least one processing circuit to produce at least one trigger signal from said processed said at least one signal; and at least one output circuit connected to at least one of the processing circuit and the trigger circuit that outputs at least one of said at least one processed signal and said at least one trigger signal, wherein said at least one register connected to said at least one channel stores a channel address of said at least one channel when said at least one channel processes said at least one signal.

2. The integrated circuit of claim 1, wherein said at least one resistance is selected from the group consisting of a resistive feedback circuit and a resistive multiplier circuit.

3. The integrated circuit of claim 1, wherein said at least one resistance is at least one resistor.

4. The integrated circuit of claim 1, wherein said at least one processing circuit is selected from the group consisting of a shaper, a fast shaper, a buffer, a pole zero, an amplifier, a transconductance, a comparator, a fast comparator, an overload comparator, a discriminator, a delay, a peak detect, a peak hold, a sample and hold, a track and hold, a time stamp, a force enable, a register, a logic, a control, a DAC (Digital-to-Analog Converter), an ADC (Analog-to-Digital Converter) and a mutiplexer.

5. The integrated circuit of claim 1, wherein said at least one output circuit is selected from the group consisting of a shaper, a fast shaper, a buffer, a pole zero, an amplifier, a transconductance, a comparator, a fast comparator, an overload comparator, a discriminator, a delay, a time stamp, a force enable, a register, a logic, a control, a DAC (Digital-to-Analog Converter), an ADC (Analog-to-Digital Converter), a multiplexer, a sample and hold, a track and hold, a peak detect and a peak hold circuit.

6. The integrated circuit of claim 1, wherein at least one input capacitor of said at least one amplifier is optimized.

7. The integrated circuit of claim 1, wherein at least one of said at least one register is used to implement a readout mode selected from the group consisting of a global, a nearest neighbor, a pixel detector and a sparse readout mode.

8. The integrated circuit of claim 1, wherein at least one of said at least one feedback circuit is external to said integrated circuit.

9. The integrated circuit of claim 1, wherein said integrated circuit further comprises at least one control logic circuit.

10. The integrated circuit of claim 1, wherein said at least one trigger circuit is selected from the group consisting of a trigger, an overload trigger, a slow trigger and a fast trigger circuit.

11. The integrated circuit of claim 2, wherein said at least one feedback circuit further comprising at least one switch.

12. The integrated circuit of claim 1, wherein said integrated circuit can be wired to another said integrated circuit in a daisy chain mode.

13. The integrated circuit of claim 1, wherein at least one delay is used with said at least one trigger signal.

14. The integrated circuit of claim 1, wherein at least two energy ranges are produced.

15. The integrated circuit of claim 1, wherein a said at least one channel can be powered down.

16. The integrated circuit of claim 1, wherein said at least one input receives said at least one signal that has at least one of the polarities positive and negative.

17. The integrated circuit of claim 1, wherein said at least one channel includes a front-end saturation detection circuit.

18. The integrated circuit of claim 1, wherein a power supplied to said at least one amplifier is adjustable.

19. The integrated circuit of claim 1, wherein said at least one processing circuit includes at least one circuit to adjust said at least one amplifier to make the said at least one amplifier perform similarly to another said at least one channel.

20. An integrated circuit comprising at least one register and at least one channel comprising at least one input, wherein at least one signal is received by said at least one input, and wherein said at least one channel comprises: at least one amplifier with at least one feedback circuit is connected to said at least one input and amplifies said at least one signal, wherein said at least one feedback circuit has at least one capacitance and at least one transistor; at least one processing circuit connected to said at least one amplifier to process said at least one signal; at least one trigger circuit connected to said at least one processing circuit to produce at least one trigger signal from said processed at least one signal; and at least one output circuit connected to at least one of the processing circuit and the trigger circuit that outputs at least one of said at least one processed signal and said at least one trigger signal, wherein said at least one register connected to said at least one channel stores a channel address of said at least one channel when said at least one channel processes said at least one signal.

21. The integrated circuit of claim 20, wherein at least one of said at least one transistor feedback is selected from the group consisting of a FET and a MosFET transistor and a CMOS circuit.

22. An integrated circuit comprising at least one channel comprising at least one input, wherein at least one signal is received by said at least one input, and wherein said at least one channel comprises: at least one amplifier with at least one feedback circuit connected to said at least one input and amplifies said at least one signal; at least one processing circuit connected to said at least one amplifier to process said at least one signal; at least one time stamp circuit connected to said at least one processing circuit to record at least one arrival time difference of said at least one signal; and at least one output circuit connected to at least one of the processing circuit and the time stamp circuit that outputs at least one of said at least one processed signal and said at least one arrival time difference.

23. A method for processing signals using an integrated circuit comprising at least one register and at least one channel comprising at least one input, wherein at least one signal is received by said at least one input, and wherein said at least one channel comprises: amplifying said at least one signal; shaping said at least one amplified signal to form at least one shaped signal; processing said at least one shaped signal; producing at least one trigger signal from said at least one shaped signal; and outputting at least one of said at least one processed signal and said at least one trigger signal, wherein said at least one register connected to said at least one channel stores a channel address of said at least one channel when said at least one channel processes said at least one signal.

24. The method for processing signals of claim 23, wherein amplifying said at least one signal comprises using at least one feedback circuit and at least one amplifier.

25. The method for processing signals of claim 23, further comprising controlling said at least one channel.

26. The method for processing signals of claim 23, further comprising producing at least one fast trigger signal.

27. The method for processing signals of claim 23, further comprising producing at least one arrival time difference.

28. The method for processing signals of claim 23, further comprising delaying processing of said at least one signal.

29. The method for processing signals of claim 23, further comprising producing at least one energy range.

30. The method for processing signals of claim 23, further comprising processing both positive and negative said at least one signal.
Description


GOVERNMENT RIGHTS NOTICE

There are no government rights on this patent application.

FIELD OF THE INVENTION

There is need for high spatial and energy resolution x-ray, gamma ray and particle detectors. Scintillation counters read out by individual photomultiplier tubes has limitations in both spatial and energy resolution. Therefore, there is need for high resolution imaging solid state sensors, as increasingly sophisticated and higher resolution detectors are needed. These new imaging sensors with large number of channels require monolithic, compact, low noise and multi-channel integrated circuits for reading out the sensors. The integrated circuit needs to be capable of matching the energy resolution coming from the detectors. A new low noise multi-channel integrated circuit has been developed which can read out high-resolution, position-sensitive sensor arrays. The developed integrated circuit has low noise, an accurate timing output and a wide dynamic range. The new integrated circuit can be used in astrophysics, nuclear medicine and physics, radiography, security, medical and industrial imaging.

The technical viability of this approach has already been demonstrated by NOVA R&D, Inc., through its current RENA (Readout Electronics for Nuclear Application) chip which has been used successfully with CdZnTe (CZT), CdTe, GaAs, Si, and Si(Li) detectors as well as gas microstrip detectors. The new ASIC is called RENA-2 and it is a major advancement over RENA.

The demand for high-performance integrated, multichannel front-end and readout electronics is commensurate with the increasingly stringent detection requirements of many NASA missions and experiments. Important instrumentation segments that the developed ASIC hopes to serve are those of advanced hard x-ray and gamma-ray telescopes and x-ray and gamma ray astrophysics in general. Certain experiments in cosmic ray astrophysics would also benefit from specific design features of the new ASIC (Application Specific Integrated Circuit).

This ASIC can be used in NASA missions such as the planned Advanced Compton Telescope (ACT), a high-priority space-based instrument, is intended to achieve significantly enhanced sensitivities for gamma rays in the 200 keV-30 MeV range. Others are the Minute-of-Arc Resolution Gamma Imaging Experiment (MARGIE) and the Energetic X-ray Imaging Survey Telescope (EXIST).

The versatile RENA-2 ASIC with wide range of features can help in advancing the present knowledge of the fluxes of energetic charged particles in space and their production mechanisms and understanding the ways in which these particles are energized and transported throughout the universe. This is fundamentally important for understanding how the cosmos functions. The new ASIC will both enable and enhance new investigations of energetic charged particles by NASA's science missions. Instruments incorporating the RENA-2 chip will be much less resource-intensive than their present-day predecessors. Replacement of the usual many strings of charge amplifier circuitry with a single chip saves volume, weight, and power. New missions, such as the miniaturized spacecraft being planned, will be greatly enhanced in their ability to measure energetic particles by RENA-2. Instruments with superior measurement capabilities will also be enabled. The new chip will allow a new generation of space flight instruments to have a large impact on imaging and understanding of x-rays, gamma rays and energetic charged particle fluxes in space.

The new chip discussed in this report can also be used for many other applications such as nuclear physics; nuclear chemistry; nuclear medicine; medical and industrial radiography; x-ray and gamma ray imaging; nondestructive evaluation (NDE) and nondestructive inspection (NDI) applications; and baggage, container, vehicle, mail, etc. scanning for security and other reasons. Medical imaging applications include high resolution solid state gamma camera and Single Photon Emission Computed Tomography (SPECT) based on the solid state gamma camera concept. Other medical imaging applications include small compact gamma camera and SPECT for small organ imaging such as breast and thyroid and/or metabolic imaging of small animals. Industrial applications include mainly NDE and NDI. Security applications include high resolution baggage, container and vehicle imaging.

BACKGROUND OF THE INVENTION

Over the past few years, solid state detectors such as silicon strip detectors have revolutionized high energy and nuclear physics research. The progress and demand for silicon strip detectors also increased in other fields where their potential high resolution detection capability became apparent. Although an excellent detector, silicon, with an atomic number (Z) of 14, does not have good quantum efficiency for higher energy x-rays and gamma rays. Therefore, recently a significant amount of research has been carried out to develop high-Z strip and pixel detectors. Out of this work, six detector materials have become the potential front runners, Germanium (needs cryogenic cooling), CdZnTe, CdTe, HgI.sub.2 and GaAs (both can be used at or near room temperature). A newcomer to the field, with very high Z, is PbI.sub.2. These materials provide high detection efficiency for x-ray energies in the 10 to 1,000 keV range with detector thickness of about 0.5 to 15 mm. One positive effect of this small thickness is that depth effects, which degrade position resolution for radiation coming in at an angle, are minimized. Consequently, these high-Z detectors are now routinely manufactured with strip or pixel sizes in the mm to sub-mm-range. Such high spatial and energy resolution two-dimensional x-ray and gamma ray sensors are expected to become the standard in the future.

Although strongly promising high-Z position sensitive solid state detectors were developed, an essential component to make them viable instruments for detecting and imaging x-rays, gamma rays and particles has been missing. Such detectors have many channels with small pitch, and reading them out with conventional discrete or hybrid electronics is not a viable option. These detectors require monolithic multichannel readout electronics to handle both the high number of channels and small pitch. Such ASIC chips, e.g., the Amplex (CERN) and SVX (LBNL) chips, have been developed for accelerator-based high energy physics experiments. However, these chips lack two major functions, which are not needed for those experiments but render the chips mostly unsuitable for use in nuclear physics, astrophysics, and medical and industrial imaging:

1. They do not have a self trigger output. In high energy physics experiments, an external machine trigger is available to inform the data acquisition (DAQ) system about the exact time of an event for reading out the chips. In addition, the event trigger is typically based on the overall event topology rather than the signal levels in individual channels, which precludes its implementation on the readout chip.

2. The solid-state detectors for which these ASICs were developed provide position information only; the energy information is largely irrelevant as the particles of interest are all minimum ionizing anyway. Consequently, such chips do not need to have low noise and thus high energy resolution capability.

By contrast, in space-based (high-energy) astrophysics as well as most medical and industrial imaging, the x-ray and gamma-ray photons and charged particles come randomly. In many applications, it is also important to measure the x-ray, gamma ray and particle energies with as high accuracy as possible. Therefore, the application of position sensitive solid state detectors to nuclear and astrophysics and to medical and industrial imaging was largely delayed as a suitable ASIC readout chip was not available. There have only been few exceptions such as the ACE chip used with silicon strip detectors on board the Advanced Composition Explorer (ACE) space mission. It is thus important to develop versatile ASICs for reading out solid state sensors for application to the above mentioned fields.

Previously we have developed a chip, called RENA (Readout Electronics for Nuclear Application) for a new scintimammography system. The RENA chip has been patented (U.S. Pat. Nos. 5,696,458, 6,150,849 and 6,333,648, incorporated herein by reference). This chip has reached a level where it was useful for imaging as well as physics research applications using various kinds of solid-state detectors; for example, it has been used successfully with silicon strip and CdZnTe pad detectors. The RENA chip is a 32-channel, mixed signal, low-noise, general purpose monolithic application specific integrated circuit (ASIC). It was developed as the front-end electronics chip for medical imaging such as gamma camera and SPECT (Kravis et al., 1999). Its dynamic range is 50,000 electrons. The chip has a self-trigger output so that random signals without an external trigger can be processed. It offers several different externally selectable integration (peaking) times to accommodate different charge collection times for different detectors. It has several readout and data acquisition modes for versatile implementation and for detailed diagnostic testing. The output signals from the 32 channels are multiplexed to a single analog output buffer under the control of the chip's readout section. Significant effort was spent to make RENA low noise (.apprxeq.150 e rms @ 0 pF input capacitance), but tests performed have indicated there are new ways to improve the noise. Also the RENA chip could only partially answer the requirements of many applications listed above. Therefore, a new ASIC, RENA-2, is developed, which can have different dynamic ranges and shaping (peaking) times, fast timing, low power consumption, lower noise, simplified user interface, and reduced channel-to-channel mismatch of the trigger levels, etc.

We describe here the new RENA-2 front-end readout ASIC designed to address these concerns and also bring significantly more functionality. The new chip is designed to be versatile and, therefore, easy to be modified and optimized for different applications, have much lower noise and thus much improved energy resolution, enabling users to take advantage of the exceptional potential for high energy resolution that solid-state detectors offer. Below the design and specifications of the new ASIC will be discussed in detail.

SUMMARY OF THE INVENTION

The design of the ASIC is guided by two principal goals. The first goal was to make the chip applicable to as wide a variety of applications as possible; this called for a flexible yet easy to use design. It has the ability to combine, on the same chip, signals that differ in terms of their polarity, rise time, threshold requirements, etc. This option, which is not available on the present RENA chip, enables users to optimize their system layout for the shortest possible signal connections, without regard to signal type. This contributed to achieving the second goal, which is equal in importance to the first, namely performance, for example, to obtain the best resolution possible for the combined detector-readout system. To reach this goal, we have designed the RENA-2 ASIC to achieve the lowest possible noise consistent with the characteristics of the detectors with which the ASIC is intended to be used.

The RENA-2 ASIC can be used with Low atomic number (Z) detectors such as silicon and carbon (diamond) as well as high atomic number (Z) semiconductor detectors such as Ge, GaAs, Selenium, CdTe, CdZnTe, PbI.sub.2, HgI.sub.2, in multi-channel strip or pixel or other geometries to detect and image x-rays, gamma-rays and particles in the range of 100 eV to 100 MeV. Other applications include reading out detectors or instruments such as Photo Diodes, Avalanche Photo Diodes (APDs), amorphous silicon detector arrays, PMTs, multi anode PMTs (MAPMTs) and VLPCs.

The features include low-noise performance, self-trigger capability, several different peaking times, different readout modes, and the daisy-chain option. New innovative features, such as user-selectable dynamic ranges and the ability to provide channel-by-channel timing information, were added. These new features, as well as the significant performance improvements required a completely new design for the new developed ASIC. The design goal for the noise performance, in particular, represents a significant improvement over the present RENA chip and substantial innovation was required in order to reach this goal. Innovation was even more urgently needed to achieve improved noise performance while reducing the chip's power consumption.

Some key specification requirements for the RENA-2 chip are shown in Table 1. For comparison, we also list the corresponding characteristics of the RENA chip. These requirements and proposed solutions for implementing the features listed in Table 1 are discussed below. Based on these requirements and solutions, a top-level design for the chip is drawn and shown in FIG. 1.

Table 1 shows the main specifications for RENA-2 ASICs. These features include the chip's low-noise performance, its self-trigger capability, and the versatility it offers by providing several different peaking times, different readout modes, and the daisy-chain option. New, innovative features include low noise, self resetting charge sensitive input amplifier, selectable multi-range shaper, user-selectable dynamic ranges, fast trigger output for coincident event detection and the ability to provide channel-by-channel time difference information. The comparator thresholds will be individually adjustable through an 8 bit DAC on each channel. This will allow accurate and uniform threshold setting throughout the detector. Two very important new features for space deployment are the adjustable power consumption by limiting the current flow to the input transistor and the radiation hardness inherent to the 0.5 micron CMOS process. The peaking times were made adjustable from about 0.4 to 40 microseconds, which makes the chip suitable for a wide range of detectors, from CdZnTe to HgI.sub.2 as listed above. The new chip incorporates a pole zero cancellation circuit to handle large rates without significant pileup. The functionality of the new RENA ASIC is dramatically improved by eliminating unnecessary connections and interface. Another important new feature is the inclusion of 4 extra channels to allow the connection of the cathode side into the same ASIC. The input amplifier is made tolerant to leakage current so that the ASIC can be used DC coupled which eliminates the need to use capacitive coupling.

The RENA chip offers the user some flexibility by providing a variety of readout modes--sparse, nearest neighbor, and global readout. The nearest neighbor mode is quite useful to account for charge sharing in strip detectors or other essentially one-dimensional detector arrays. However, its successful application requires a monotonic mapping of detector strips to RENA channels, which is not always optimal from the point of view of interconnect capacitance or mechanical constraints. In addition, extension of the nearest neighbor mode to two-dimensional arrays, though equally desirable, is not possible, simply because there is no "natural" mapping from the four to eight nearest neighbors of a given pixel to the sequence of channels on the readout chip. Instead, RENA-2 provides the user with high flexibility that is the ability to specify which channels are to be read on a case-by-case basis. In this scenario, the readout pattern is controlled by a serial shift register with one bit per channel; if a bit is set, the corresponding channel is read out. Initially, when a channel triggers, the corresponding bit in the readout register is set. Before reading out the detector data, the control logic can inspect the trigger pattern and, if necessary, replace it with a different readout pattern. This operation can be completed in 2.3 .mu.s (for 36 channel ASIC), regardless of the total system channel count, with a suitably designed external controller FPGA; it need not significantly compromise the dead time specification. The readout pattern can be a nearest neighbor pattern customized to the particular experimental setup. This gives significant flexibility for application to a variety of detectors of different configurations such as pixel and strip detectors.

TABLE-US-00001 TABLE 1 Key requirements and suggested features for the design of the RENA-2 ASIC. For comparison, the corresponding characteristics of the existing RENA ASIC are also listed. Specification RENA-2 ASIC RENA ASIC Signal range Two full-scale ranges; 50 and 250 ke, Fixed, typically 50 ke full selectable for each channel (Other ranges scale are possible.) Input polarity + or - (Selectable channel-by-channel) + or - (Selectable for the whole ASIC) Number of 36 Channels (Extra channels added to 32 Channels channels allow connection of the cathode electrode) Noise Minimize noise (18 aC (112 e) rms in the Minimize noise 9 fC signal range and 45 aC (280 e) rms in the 53 fC range) Noise 2 pF and 9 pF detector capacitance 6 pF detector capacitance optimization DC leakage Minimize effects and to be tolerant Not allowed above pico current Amps region Power Adjustable. (Minimize power through Not adjustable but designed consumption adjustments to the current supplied to parts to be reasonable of the circuit) Fast timing output Low jitter (Minimize jitter as far as Not available possible) Channel-to- Implemented Not implemented channel time difference Input amplifier Fixed resistance with or without resistance None resistive feedback multiplier and/or MosFET based resistance Trigger Individually adjustable by internal 8 Bit Externally adjustable for the comparator DACs for each channel whole chip thresholds Peaking times 0.4 to 40 microseconds in 16 steps 0.4 to 6 microseconds in 8 steps Fast count rates Using pole zero cancellation Not available Detector structure Heterogeneous (or homogeneous) Homogeneous Key gamma 1 keV, 6 keV, 14 keV, 60 keV, 141 keV, 14 keV, 60 keV, 141 keV signals 511 keV, 662 keV, 1.33 MeV and up to 10 MeV System Pipeline A/D converter, FPGA state A/D converter or PC-based components machine controller, data FIFO A/D board, control software on PC or microcontroller Interface Minimum pin count and support Simple protocol component count Readout mode Maximum flexibility through hit register Simple protocol Dead time per Minimize as far as reasonable (Reset is Not minimized event much faster.) Radiation Minimize radiation damage effect about 0.1 Not considered tolerance to 1 MRad

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a preliminary block diagram of the developed new ASIC. Only one channel (channel k) is shown; connections to adjacent channels are indicated where applicable; the slow and fast signals are shown multiplexed here but in one embodiment separate comparators can be used for the slow and fast signals from the analog section.

FIG. 2 is a block diagram of the analog section of the RENA chip

FIG. 3 is four RENA hybrids mounted onto a printed circuit board. The resistors and capacitors are mounted onto or fabricated on the ceramic carrier to produce high quality AC coupling to the detector channels.

FIG. 4 is a CdZnTe 8.times.4 2-D pad detector array used to obtain the x-ray spectra as described in the text. Pad pitch is 3.times.3 mm.

FIG. 5 is a graph of input referred noise vs. input pulse height. Three curves are shown for 0, 3, and 9 pF capacitances. The measurement was performed with the capacitor directly connected to the RENA chip input.

FIG. 6 is a graph of RENA chip linearity measurement. Output voltage vs. input test pulse height. The deviation from a linear fit is indicated by the triangles, with the scale shown on the right hand side.

FIG. 7 is a spectrum of .sup.241Am obtained with a CdZnTe pad detector (FIG. 4) connected to a RENA chip.

FIG. 8 is a spectrum of .sup.57Co obtained with a CdZnTe pad detector (FIG. 4) connected to a RENA chip.

FIG. 9 is a spectrum of .sup.241Am obtained with a Hamamatsu S5972 Si photodiode mounted onto a prototype RENA chip. The energy scale on the lower x-axis was obtained from the calibration shown in FIG. 10.

FIG. 10 is an energy calibration of a Hamamatsu S5972 Si photodiode obtained using various x-ray and gamma ray lines of .sup.57Co, .sup.139Ce, and .sup.241Am.

FIG. 11 is a block diagram of the typical signal characteristics and analog signal processing of the RENA-2 chip.

FIG. 12 is a single channel block diagram for the analog section of the RENA-2 integrated circuit.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to the ASIC described in FIG. 1 a detector 10 is connected to the input of the ASIC and the input goes to an analog signal processing unit 11. The FIG. 1 shows only one of the analog channels of the ASIC, the k channel. Analog processing unit is described below. Peak detector output of the analog signal processing unit 11 goes to analog output buffer amplifier 19 through a switch 41 controlled by read sequence logic 23. The peak detect output is also attached onto a bus 40 before it enters analog output buffer 19. Analog output is made available to the outside world as an output 26 of the ASIC. A test input 13 is used to test the analog signal processing unit. An overload sensing element 12 is connected to the analog signal processing unit 11. Output of the overload sensor 36 is provided to outside world as an output of the ASIC.

Analog signal processing unit 11 outputs a slow and fast shaper signal during processing of the signal from the detector 10 which go into a multiplexer 14. Output of the multiplexer 14 goes into a comparator 15. In another embodiment shown in dotted lines the fast shaper output goes separately into a fast comparator 17, whose output goes out to the outside world as the timing trigger output 25. Similarly the slow shaper output from the analog processing unit 11 goes separately to the comparator 15. The threshold of comparator 15 is adjusted through threshold DAC 18. The threshold DAC 18 is set by the external control computer through the configuration control logic, not shown. The output of the comparator 15 is gated (or AND circuit) 16 by using an enablek signal. The output of the gate 16 goes to an OR circuit 20. The gated comparator 16 outputs from other analog channels also come to the OR circuit 20. The output of the OR circuit is send outside the ASIC as the event trigger 27. The output of the gate 16 also goes to the gate 21 and flip flop 24 which controls the switches 42.

An acquire 37 signal is sent by the data acquisition computer to the ASIC. This signal is routed inside the ASIC to analog signal processing unit 11 and to hit/read shift register 22 through a gate 21. The gate or AND circuit 21 is controlled by the output of the gated comparator 16. The output of the gate 21 is used to set the k.sup.th channel of hit/read shift register (signal is called set.sub.k) when there is signal in that channel from the detector 10 which has produced a trigger signal comparator 15 and gate 16. The hit/read shift register is controlled by external signals HRDI 28 (hit/read data input) and HRDO 29 (hit/read data output). The output of the hit/read shift register 22 goes to read sequence logic 23. The read sequence logic circuit is controlled externally through an external signal NEXT 30 and also in general through configuration control logic not shown. Read sequence logic controls all the other channels similar to the k.sup.th channel shown in FIG. 1. Read sequence logic 23 also controls the switches 43 which control the output of the time difference measurement circuit as explained below.

There is a time difference measurement circuit which measures the difference of the arrival time of detector 10 signals at each channel. This circuit has two sign wave inputs V.sub.u Input 31 and V.sub.v Input 32. The phase of these two sign waves are at an angle, such as 90 degrees, to each other. These inputs are common to all channels and enter a bus 38 for V.sub.u Input 31 and bus 39 for V.sub.v Input 32. The distributes the sign waves to all the channels. At each channel flip flop 24 controls the switches 42 which allow the sign waves to charge separate capacitors at the input of amplifiers 33 and 34. The amplifier circuits 33 and 34 produce a voltage level at its output depending on the time the switches 42 are closed. If voltage levels from different channels which had data output by the amplifiers 33 and 34 for each channel are compared then a relative arrival time difference between the ASIC channels can be determined. The output of the amplifiers 33 and 34 go to a readout bust 35 through switches 43 controlled by the read sequence logic circuit 23.

In FIG. 1 the configuration control logic circuit 23 is not shown. This is a digital circuit which controls the ASIC analog data readout. All the signals shown in FIG. 1 are single ended. However, in the ASIC some of these are made differential when ever necessary.

The analog circuit inside the analog signal processing unit 11 is similar to given in FIG. 2. It contains a detector input 50, test input 51, shaper 54, peak detector 55, overload comparator 58. The other comparators 15 and 17 are already discussed above. There may be a polarity amplifier 53 or other buffer amplifiers such as polarity amplifier 53. There is also a pole zero circuit after input amplifier 52 or anywhere else in the chain if better, not shown. The pole zero circuit can be switched on or off as necessary. Pole zero circuit reduces the pile up effect and thus increases the ASIC throughput rate.

The RENA chips are shown in FIG. 3. The detectors 70 are mounted on the end of the chip carrier 73 through coupling capacitors 71. The RENA chip 72 is mounted on the chip carrier 73. The chip carrier is mounted on top of the printed circuit board 74. The whole system shown in FIG. 3 forms a imaging detector unit with a total of 128 pixels, 4.times.32 array.

FIG. 4 shows the CdZnTe 84 detector 80 used. The 4.times.8 array of pixels 83 are shown. The pixels are connected to the input of the ASIC input amplifier 81 through capacitative coupling 82. In RENA-2 due to self resetting type of input amplifier there will be no need for capacitative coupling 82 for most detectors and DC coupling will be used.

The signal range needs to be adjusted to meet the requirements of the various sensors that we intend to use with the RENA-2 chip. Different experiments may need widely varying energy ranges. We have implemented an adjustable signal range on the RENA-2 chip. One way to do this is to make the circuit components that control the signal range to be switchable. The two ranges built in are 9 fC and 53 fC, corresponding to photon energies of 250 keV and 1.5 MeV in CdZnTe (CZT), respectively (based on the typical energy of 4.4 eV required to create one electron-hole pair in CZT). The switching between the two ranges will be controlled, on a channel-by-channel basis, by an on-chip control register.

The RENA-2 readout chip is designed to have significantly lower noise and thus much improved energy resolution compared to the present RENA. This is an important and essential improvement that will significantly enhance the chip's usefulness for all kinds of applications. We designed for input-referred noise values of approximately 18 aC (112 e) rms in the 9 fC signal range and 45 aC (280 e) rms in the 53 fC range, for dynamic ranges of 500 and 1200, respectively. In order to accomplish the latter goal over the wide range of detector capacitances, we incorporated into the design two selectable different widths for the input transistor, for the noise optimization, using a control bit (again on a channel-by-channel basis). The new chip is optimized for the noise level for detector capacitances of 2 pF and 9 pF, respectively. With the lower detector capacitance, we expect to achieve a somewhat improved noise performance in the 53 fC range compared to the value given above, possibly 35 aC (220 e) rms.

We have performed the following steps in the effort to optimize the energy resolution of the new ASIC.

1. Low-noise CMOS process that have low 1/f noise is used.

2. The noise that may be injected by the peak/hold and digital electronics sections are minimized.

3. The design of the input amplifier and the shaper amplifiers are improved.

4. Reducing the gain of the input amplifier also can improve its tolerance of DC input current.

5. A self resetting type input amplifier is designed to increase tolerance to detector leakage current. This eliminates the need for AC coupling and consequently higher capacitance (and therefore higher noise), as well as errors due to recovery of the AC coupling network from prior events.

6. The silicon layout is improved so that it would make the analog section less susceptible to cross talk from the rest of the circuit and also to external noise pickup.

7. To further remedy the effect of baseline differences, we have used a DAC on each channel to set the threshold. The full-scale range of the threshold DACs is given by a reference voltage common to all channels (VTR in FIG. 1). This adds flexibility by allowing the DAC range and resolution to be adjusted to the requirements of specific experiments.

The dynamic range is adjustable or selectable to meet the requirements of the various sensors that we intend to use with the new readout chip. Different experiments may need different energy ranges. The dynamic range is made adjustable for the new chip. One way to do this is to make the circuit components that control the dynamic range to be switchable. Other options, such as controlling the dynamic range through an externally supplied voltage or current, is also possible.

One factor that currently limits the RENA chip's dynamic range more than the noise itself is the lack of any possibility to adjust baseline levels between the channels or alternatively adjust the trigger thresholds to compensate for any baseline difference. This means that the effective trigger threshold, in terms of photon energy, will differ from channel to channel and will be limited by the channel with the highest baseline level. A significant contribution to the baseline differences could come from variations in charge injection in the process of resetting the signal channels after an event. The levels clamped to during the reset process have been found to vary significantly less from channel to channel than those observed after the release of the reset switches. By improving the reset circuitry, the variability of baseline levels will be reduced.

To further remedy the effect of baseline differences, we used a DAC on each channel to set the trigger comparator threshold. The full-scale range of the threshold DACs is given by a reference voltage common to all channels. This adds flexibility by allowing the DAC range and resolution to be adjusted to the requirements of different experiments. Similarly DACs will be used to set the thresholds for the fast trigger comparators, which will give the fast or time accurate low jitter trigger and/or timing signal output.

An important application field for the developed ASIC chip will be space-based astrophysics experiments, where power consumption is an important issue. The major part of the power is consumed in the input transistor. Therefore, the current flow into the input transistor is made externally adjustable, thus allowing the capability of reducing the power of the ASIC. A large current flowing in the input transistor is essential for the low noise response of the new chip. However, our design and layout changes aimed at further noise reduction (discussed above) do not involve increasing that current flow. Thus, developing the highest possible energy resolution for the new ASIC chip will allow us more room for compromise in cases where ultra-low noise is less important than low power consumption.

Throughout the rest of the analog and digital circuits, where lowering the power consumption will not affect the noise performance of the chip, we will develop circuits with lowest possible power consumption for the selected fabrication process. This will allow the development of the new ASIC specifically for space-based astrophysics and other power-critical applications.

Many sections of the chip such as each channel, channel to channel time difference circuit, fast trigger circuit are designed so that user can externally power down the unused sections of the circuit, that is their power can be cut to reduce the power dissipated by the chip. All these are essential for power critical applications such as space based detectors, where all unused features can be turned off to reduce the power consumption of the new ASIC.

Information about the signal timing is important in many experiments, especially when coincidence measurements (between separate interactions in different parts of the instrument or between signals from different electrodes of the same detector) are required. Therefore, we plan to record information related to signal timing and make it available for readout together with the pulse height data. Since we anticipate a wide variety of range and resolution requirements for the time information, it will not be practical to incorporate full-fledged time-to-digital (or time-to-amplitude) converters on the ASIC. We made each channel to produce a low jitter fast trigger signal output 25 using a fast comparator (discriminator), which is multiplexed to produce a single timing output or they may even be made available separately for each channel although this would require large number of signal pads. To take full advantage of this new feature, the trigger output jitter is improved to achieve high resolution signal timing. We did this by adding to the signal path a second, fast shaper with low jitter optimized for timing rather than energy resolution and using this shaper to generate the trigger signal. Alternatively, to avoid the increased die space and power consumption that this solution would require, the timing resolution can be improved by tapping the trigger signal off of the first shaper stage(s).

We have also incorporated into the design a channel to channel event arrival time difference measurement circuit. Two inputs are provided for two user-provided analog signals (V.sub.u and V.sub.v) whose momentary values will be stored for readout in channel-specific sample-and-hold circuits whenever the respective channel's trigger comparator fires. The known time dependence of these external signals, which can be optimized for the specific application, can then be used to reconstruct the actual timing information. Examples of suitable external signals include sinusoidal waveforms, with a 90.degree. phase difference to resolve ambiguities, or linear ramps that are initiated by the first channel trigger for any given event.

In the RENA-2 chip we have designed every channel separately and externally switchable to either input polarity; negative (electrons) or positive (holes). Placement of the polarity switch is changed from just after the charge sensitive amplifier 52 at the input to before, inside or after the peak hold (detect) 55 circuit.

In the RENA-2 chip we have designed several different types of feed back circuit for the charge sensitive input amplifier 52. The different feedback circuits incorporated into every channel can be selected by the user for application to different instruments and devices. These feedback circuits are:

1. Resistance placed internal or external to the ASIC.

2. Resistance multiplier placed internal to the ASIC.

3. Any type of resistance with an integrating capacitor placed internal or external to the ASIC.

4. A MOSFET transistor resistance circuit.

5. Integrating capacitor.

6. Any or all of the above feedback combinations with a reset switch.

The RENA chip offers the user some flexibility by providing a variety of readout modes --sparse, nearest neighbor, and global readout. The nearest neighbor mode is quite useful to account for charge sharing in strip detectors or other essentially one-dimensional detector arrays. However, its successful application requires a monotonic mapping of detector strips to RENA channels, which is not always optimal from the point of view of interconnect capacitance or mechanical constraints. In addition, extension of the nearest neighbor mode to two-dimensional arrays, though equally desirable, is not very practical, simply because there is no "natural" mapping from the four (or six, for a hexagonal detector array) nearest neighbors of a given pixel to the sequence of channels on the readout chip. Other schemes, such as reading out the (single) cathode of a detector whenever one of the anode pixels triggers (or vice-versa), are equally difficult to anticipate.

Instead, in the RENA-2 chip we have provided the user with the ability to specify which channels are to be read on a case-by-case basis. In this innovative new technique, the readout pattern is controlled by a serial shift register 22 with one bit per channel; if a bit is set, the corresponding channel is read out. Initially, when a channel triggers, the corresponding bit in the readout register is set. Before reading out the detector data, the user can then inspect the trigger pattern and, if necessary, replace it with a different readout pattern. This operation can be completed in 2.1 .mu.s (for 32 channel ASICs), regardless of the total system channel count, with a suitably designed external controller FPGA; it need not significantly compromise the dead time specification. The readout pattern can be a nearest neighbor pattern customized to the particular experiment setup, a global readout (by setting every bit in the readout register), or any other pattern that may be needed for the specific situation. While it would seem at first glance that offering this mask read/write capability would increase the complexity of the ASIC's user interface, the opposite is actually true: The logic and interconnect resources required to implement the nearest neighbor mode alone, especially across multiple chips, is more complex than the readout shift register technique.

The RENA-2 chip can be also set up to automatically disable additional triggers about 50 ns or more delay after the initial trigger. This time delay is useful to allow multiple simultaneous or nearly simultaneous input signals of varying pulse height to reach the full pulse height for correct energy measurement.

In addition to the 32+4=36 signal channels, the RENA-2 chip has two analog-only isolation channels, one each on either end of the analog channel group. One or both of these isolation channels, can be used to measure correlated noise during an event and they also have test points where a probe can be used to have access to signals inside the analog channel at critical points.

In summary, we have developed a RENA-2 ASIC readout chip designed to accommodate a wide range of position sensitive or multi array solid-state x-ray and gamma ray detectors to be used in space-based astrophysics and/or in many other commercially important applications. Our main goal is to produce a readout system that will enable its user to take full advantage of the good energy resolution offered by these detectors. The result is a new ASIC chip optimally suited for space-borne astrophysics experiments, and medical and industrial imaging instruments that plan to image x-rays, gamma rays and charged particles with high energy and spatial resolution.

Test Results

The RENA chip is a charge-sensitive 32-channel mixed signal ASIC; its specifications are shown in TABLE 2. The present version has a dynamic range of 50,000 electrons and maximum output swing of 2 V. The input is single-ended with the input amplifier referenced to an external low-noise reference voltage. The output signals from the 32 channels are multiplexed to a single analog output buffer under the control of the chip's readout section.

A block diagram of the analog signal path for one of the 32 channels is shown in FIG. 2. The first stage of the signal path, AMP1, is a switched-reset integrator 52. The input amplifier 52 is designed to have a large open loop gain, to reduce noise and improve the response to high input capacitance sensors. A calibration input 51 to AMP1 allows simple testing of analog channels using an external signal source. The second stage of the signal path is a polarity amplifier 53, which amplifies the signal from the first stage and has a control to select a positive or negative gain. This feature allows RENA to be used with both electron- and hole-collecting detectors. The shaper 54, which follows the polarity amplifier 53, is a first order transconductance-C bandpass filter with programmable bandwidths. These bandwidths are selected through three bits in the chip's configuration shift register. The filtered signal is peak-detected 55 in the following stage. During readout, the peak-detectors 55 are isolated from the shaper by a switch, to avoid spurious signals from late hits.

Two comparators 57 and 58 sense the output level of the peak detector 55. The threshold comparator 57 generates the trigger signal that is then used in the channel logic. The overload comparator 58 may be used, for example, to sense a high-energy event or detect events inside an energy window. The channel outputs from either comparator are OR'ed to pads TRIG and OL 60, respectively; in addition, the individual outputs from the threshold comparator are used by the readout logic to determine which channels need to be read. The thresholds for the two comparators are controlled by the external voltage levels supplied through pads THS and THO. The peak-detected signals from all channels being read are multiplexed to an output amplifier connected to output pad AOUT. This output amplifier is tri-stated when the RENA chip is not being accessed. This allows the output amplifiers of several (daisy-chained) chips to share a common analog output bus. For test purposes, any channel can be continuously connected to AOUT ("Force Enable Mode").

In addition to the 32 signal channels, RENA has two analog-only isolation channels, one each on either end of the analog channel group. Channel 33, the isolation channel at the `high` end of the chip, can be used to measure correlated noise during an event.

TABLE-US-00002 TABLE 2 RENA chip specifications. Number of channels 32 + two test channels Readout modes Sparse readout: Readout is limited to channels whose signal level is above the trigger threshold Neighbor readout: Sparse readout, with additional readout of channels adjacent to triggered ones Global readout: Read all enabled channels in response to any trigger Select all: Read all enabled channels on an external trigger pulse Trigger threshold Voltage input, 1.5 V to 3.5 V Trigger disable Automatically after a trigger, or in response to an external signal Readout data Channel and chip addresses, pulse height and high threshold set bit Readout time .apprxeq.800 ns per channel Daisy chain Up to 16 chips can be daisy chained to be read out as a single chip Power 200 mW per chip Test output modes Enable any one channel for continuous output Peaking time 0.4, 0.73, 1.06, 1.34, 1.73, 3.17, 4.61 or 6.05 .mu.s Dynamic range .apprxeq.1 ke to 50 ke input for 1.5 to 3.5 V output Input referred noise .apprxeq.150 e rms @ 0 pF with 8 e rms/pF slope Die size 4.9 .times. 6.9 mm.sup.2

The RENA chip has several different readout modes, as shown in Table 2. In the "sparse" mode, only channels that are triggered (have a signal above the threshold of the low-level comparator) are read out. In the "neighbor" mode, the nearest (adjacent) channels immediately above and below any channel that has valid data are also read out. This mode is important if charge sharing between detector channels is expected to happen with significant probability. In the "global" mode, all channels are read out in response to a trigger. The "select all" mode allows an external trigger to initiate readout of all channels. In all modes, triggering and readout can be disabled for any channel. Once a channel is triggered, any additional triggers on the chip should be disabled during readout in order to avoid spurious coincidences. This is accomplished by an external signal that must be supplied to the TDIS input, after a suitable delay to account for pulse-height dependent time walk and different charge collection times from truly coincident signals. Alternatively, the chip can be set up to automatically disable additional triggers about 50 ns after the initial trigger.

Up to sixteen RENA chips can be daisy-chained together and read out as if they form a single chip with up to 512 channels. This is advantageous for detectors, which have more than 32 channels. For example, a strip detector with 128 strips on each side can be read out by four RENA chips on each side daisy-chained together.

This section describes tests of the RENA chips that have been performed at NOVA. Those tests that required actual x-ray detector signals were carried out using two-dimensional CdZnTe pad detector arrays. Details of the setup and the test results are discussed below.

FIG. 3 shows four RENA chip ceramic hybrids soldered onto a printed circuit board. Detectors (FIG. 4) can be connected to the hybrids via standard connectors. The hybrids were designed to abut with each other so that a long chain of detectors can be made.

The energy resolution for CdZnTe pad detectors is excellent because of the large number of electron-hole (e-h) pairs created. Approximately one e-h pair is produced per 4.4 eV energy R.sub.I=.DELTA.E/E=2.35/ {square root over (N)} deposited. Assuming a Poissonian distribution, the limiting resolution R.sub.I (FWHM), due only to statistical fluctuations in the number of charge carriers, can be calculated according to

where N is the number of e-h pairs created (Knoll, 1989). For example, an x-ray photon with an energy of E.sub.0=100 keV which is absorbed via the photoelectric effect generates about 22,700 e-h pairs in CdZnTe, from which we obtain R.sub.I=1.5%.

The limiting energy resolution for 60 keV x-rays can be calculated similarly to be .apprxeq.2% (or 1.2 keV). This shows that there is room to improve the





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