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Title: Power losses reduction in switching power converters

Abstract: Embodiments of the invention provide methods and apparatuses for concurrently eliminating or substantially reducing two or more switching losses in an inverter switching circuit. Embodiments of the invention concurrently reduce multiple types of switching losses under hard switching mode and soft switching mode for active switching devices and diodes. In one embodiment of the invention, the voltage across a switching device is substantially reduced during switch turn-off and/or turn-on time, and also maintained at a substantially reduced level throughout some or all of the tail current loss time of the switching device. Other methods and apparatuses are also described.

Patent Number: 7,417,409 Issued on 08/26/2008 to Partridge

Inventors: Partridge; Donald F. (Los Gatos, CA)
Assignee: One More Time LLC (Los Gatos, CA)
Appl. No.: 11/369,445
Filed: March 6, 2006
Related U.S. Patent Documents
Application NumberFiling DatePatent NumberIssue Date
60659599Mar., 2005

Current U.S. Class: 323/222
Current International Class: G05F 1/10 (20060101)
Field of Search: 323/222,223,225,233 363/50,55,56.12

References Cited [Referenced By]
U.S. Patent Documents
3652874 March 1972 Partridge
5399908 March 1995 Donaldson
5448465 September 1995 Yoshida et al.
5570276 October 1996 Cuk et al.
6051893 April 2000 Yamamoto et al.
6757184 June 2004 Wei et al.
7113575 September 2006 Orr
7148662 December 2006 Kato
Foreign Patent Documents
2 324 661 Oct., 1998 GB
WO 01/73948 Oct., 2001 WO

Other References

J Holtz, et al., "High-power pulsewidth controlled current source GTO inverter for high switching frequency," Industry Applications Conference, 1997, vol. 2, pp. 1330-1335 (Oct. 5, 1997). cited by other .
PCT Notification of Transmittal of The International Search Report and the Written Opinion of the International Searching Authority or The Declaration for PCT Counterpart Application No. PCT/US2006/008292 Containing International Search Report (Oct. 31, 2006). cited by other .
PCT Notification of Transmittal of International Preliminary Examination Report on Patentability for PCT Counterpart Application No. PCT/US06/08292, 4 pgs. (Feb. 27, 2008). cited by other.

Primary Examiner: Nguyen; Matthew V
Attorney, Agent or Firm: Blakely, Sokoloff, Taylor & Zafman LLP
Parent Case Text


RELATED APPLICATIONS

This application claims the benefit of U. S. Provisional Application No. 60/659,599, entitled "Methods and Apparatuses to Reduce Power Losses in Switching Power Converters", filed Mar. 7, 2005, which is hereby incorporated by reference in its entirety.
Claims


What is claimed is:

1. A power switching circuit, comprising: a first switching device; a first voltage source electrically coupled to the first switching device, the first voltage source providing a normal operational voltage for the power switching circuit; and a switching voltage reduction mechanism coupled to the first switching device and the first voltage source for substantially reducing a voltage across the first switching device, relative to the normal operational voltage, prior to and during at least a portion of a turn-on time of the first switching device, wherein the switching voltage reduction mechanism is also configured to reduce the voltage across the first switching device during a turn-off time of the first switching device, and wherein the switching voltage reduction mechanism is configured to maintain a substantially reduced voltage across the first switching device during at least a portion of a tail current loss time of the switching device.

2. The power switching circuit of claim 1, wherein the first switching device is a bi-polar device.

3. The power switching circuit of claim 1, wherein the first switching device is selected from the group consisting of a bi-polar transistor, an insulated gate bi-polar transistor, a gate turn-off thyristor, a silicon-controlled rectifier device, and an integrated gate commutated thyristor.

4. The power switching circuit of claim 1, wherein the first switching device comprises multiple switching devices including a third switching device and a fourth switching device, wherein the switching voltage reduction mechanism is configured to substantially reduce the voltage across the third and fourth switching devices when the third switching device is being turned on while the fourth switching device is being turned off.

5. The power switching circuit of claim 1, wherein the switching voltage reduction mechanism further includes a saturable reactor electrically serially implemented between the voltage source and the first switching device, the saturable reactor effecting the substantially reduced voltage across the first switching device during the turn-on time of the first switching device.

6. The power switching circuit of claim 5, further comprising a resistor implemented in parallel with the saturable reactor to limit current flow through the first switching device during a conductivity modulation loss time of the first switching device.

7. The power switching circuit of claim 1, wherein the switching voltage reduction mechanism effects substantially reduced voltage across the switching device by bypassing a current through the switching device.

8. The power switching circuit of claim 7, wherein the switching voltage reduction mechanism is implemented as a switching device in parallel with the switching device.

9. The power switching circuit of claim 8, wherein the switching device is a field effect transistor.

10. The power switching circuit of claim 7, wherein the switching voltage reduction mechanism is implemented as a capacitor in parallel with the switching device.

11. The power switching circuit of claim 6, wherein the voltage reduction mechanism provides a substantially reduced voltage source such that switching of the first switching device is effected at a substantially reduced voltage.

12. The power switching circuit of claim 11, wherein the substantially reduced voltage source is a second voltage source implemented as an independent voltage source separated from the first voltage source.

13. The power switching circuit of claim 11, wherein the voltage reduction mechanism is implemented as a transformer circuit electrically serially implemented between the voltage source and the switching device.

14. The power switching circuit of claim 13, wherein the transformer circuit refers a first current to a primary windings of a transformer and a second current to a load of the switching circuit such that a short-circuit current is limited to the first current.

15. The power switching circuit of claim 11, wherein the voltage reduction mechanism is implemented as a parallel resistor-capacitor circuit electrically serially implemented between the voltage source and the switching device.

16. A method, comprising: substantially reducing a voltage across a first switching device of a power switching circuit, relative to a normal operational voltage for the power switching circuit, prior to and during at least a portion of a turn-on time of the first switching device, the normal operational voltage provided by a first voltage source of the power switching circuit; substantially reducing the voltage across the first switching device of the power switching circuit, relative to a normal operational voltage for the power switching circuit, during a turn-off time of the first switching device; and maintaining the voltage across the first switching device at a substantially reduced level during at least a portion of a tail current loss time of the first switching device, wherein the voltage across the first switching device during the turn-on and turn-off time is controlled by an identical switching voltage reduction mechanism.

17. The method of claim 16, wherein the first switching device comprises multiple switching devices including a third switching device and a fourth switching device, wherein the switching voltage reduction mechanism is configured to substantially reduce the voltage across the third and fourth switching devices when the third switching device is being turned on while the fourth switching device is being turned off.

18. The method of claim 17, further comprising substantially reducing a current through the switching device, relative to a normal operational current, during a conductivity modulation time of the switching device.

19. The method of claim 16, wherein the switching device is a bi-polar device.

20. The method of claim 19, wherein the switching device is selected from the group consisting of a bi-polar transistor, an insulated gate bi-polar transistor, a gate turn-off thyristor, a silicon-controlled rectifier device, and an integrated gate commutated thyristor.

21. The method of claim 16, wherein substantially reducing a voltage across the first switching device, relative to the normal operational voltage, during a turn-on time of the first switching device is effected by implementing a saturable reactor electrically serially between the voltage source and the first switching device.

22. The method of claim 18, wherein substantially reducing a current through the switching device, relative to a normal operational current, during a conductivity modulation time of the switching device is effected by implementing a resistor implemented in parallel with the saturable reactor to limit current flow through the switching device during a conductivity modulation loss time of the switching device.

23. The method of claim 16, wherein substantially reducing a voltage across the switching device of the power switching circuit is effected by bypassing a current through the switching device.

24. The method of claim 23, wherein bypassing the current through the switching device is effected by implementing a high-speed switching device in parallel with the switching device.

25. The method of claim 24, wherein the high-speed switching device is a field effect transistor.

26. The method of claim 23, wherein bypassing the current through the switching device is effected by implementing a capacitor in parallel with the switching device.

27. The method of claim 18, wherein substantially reducing a voltage across a switching device of the power switching circuit is effected by providing a substantially reduced voltage source and switching the switching device at a substantially reduced voltage.

28. The method of claim 27, wherein the substantially reduced voltage source is implemented as an independent voltage source.

29. The method of claim 27, wherein substantially reducing a voltage across a switching device of the power switching circuit is effected by implementing a transformer circuit electrically serially between the voltage source and the switching device.

30. The method of claim 29, further comprising referring a first current to a primary windings of a transformer of the transformer circuit, the first greater than a second current to a load of the switching circuit, such that a short-circuit current is limited to the first current.

31. The method of claim 27, wherein substantially reducing a voltage across a switching device of the power switching circuit is effected by implementing a parallel resistor-capacitor circuit electrically serially between the voltage source and the switching device.

32. An apparatus, comprising: means for substantially reducing a voltage across a first switching device of a power switching circuit, relative to a normal operational voltage for the power switching circuit, prior to and during at least a portion of a turn-on time of the first switching device, the normal operational voltage provided by a voltage source of the power switching circuit; means for substantially reducing the voltage across the first switching device of the power switching circuit, relative to a normal operational voltage for the power switching circuit, during a turn-off time of the first switching device; and means for maintaining the voltage across the first switching device at a substantially reduced level during at least a portion of a tail current loss time of the first switching device, wherein the voltage across the first switching device during the turn-on and turn-off time is controlled by an identical switching voltage reduction circuit.
Description


FIELD OF THE INVENTION

The present invention relates generally to power converters. More particularly, this invention relates to power losses reduction in switching power converters.

BACKGROUND

Power converters are employed in electronic equipment to control power delivered to a variety of loads. Power input is typically 50 or 60 Hz at standard voltages such as 110V, 220V, 440V, 2.4 kV, 3.3 kV, etc. Power converters are used to rectify the input voltage into a DC level; an inverter is then used to invert the DC voltage to an AC voltage. Industrial uses involving varying the frequency and the voltage magnitude.

Circuits used to invert the DC voltage employ switching devices which are turned on and off with a prescribed modulation pattern. This provides an output signal having a desired frequency and magnitude. For example, a typical modulation pattern that may be employed is pulse width modulation (PWM). PWM alters the width of the conduction waveform of the switching devices so that, after filtering, output voltage varies from a positive peak voltage through 0 volts to a negative peak voltage thereby producing an alternating voltage output.

Typical switching circuits employed in an inverter circuit include bi-polar transistors, insulated gate bi-polar transistors (IGBTs), gate turn-off thyristors (GTOs), silicon-controlled rectifier devices (SCR's) and integrated gate commutated thyristors (IGCTs), among others. Such switching circuits incur several types of losses including switching device losses and freewheeling diode losses (for inductive inverter circuits).

Switching Device Losses

Switching device losses include two main sources, switching loss and conduction loss. Conduction losses are the normal losses of the switching device while conducting current when running in a saturated condition. Switching losses are the losses associated with the actions of turning active switching devices on and off. Switching losses occur when there is simultaneously, high voltage across the device and current through it during transitions between on and off. Typically a power converter uses PWM with the switching device used in so-called "hard switching" mode (HSM). HSM refers to switching in which the inverter switching devices block voltage while simultaneously conducting current during transition between on and off. Power loss is incurred during this period of simultaneous voltage across the device and current through the device. This power loss is referred to as VI turn-on loss and VI turn-off loss to indicate, that for HSM, power loss is incurred each switching cycle during the turning on and turning off of the switching device. Because switching losses are incurred every time the device turns on and off, higher device frequencies result in greater switching losses.

Losses associated with turning the switching device on include the VI turn-on loss, conductivity modulation loss (for bipolar device) and capacitance discharge loss, while losses associated with turning the switching device off include the VI turn-off loss and tail current loss (in some device under certain conditions).

Diode Losses

The diode of the inductive inverter circuits incurs conduction losses (typically a function of device design and current), conduction modulation losses (incurred when the switching device is turned on), and reverse recovery losses (incurred when the switching device is turned off).

Typical losses are described more fully below in reference to FIG. 1, which illustrates a hard switching circuit in accordance with the prior art. Switching circuit 100, shown in FIG. 1 is an HSM circuit, which may be used to explain the noted sources of switching losses. Switching circuit 100 includes an IGBT switching device 105 with its collector 106 connected to the positive end 111 of a DC source voltage 110 having a voltage value of E volts. The emitter 107 of the IGBT switching device 105 is connected to an inductor 115 representing the lead inductance in series with the IGBT switching device 105. The inductor 115 is in-turn connected to inductors 120 and inductor 130.

Inductor 120 represents the lead inductance of diode 125 and is in-turn connected to the cathode 126 of diode 120. Inductor 130 is a large filter inductor and is connected in-turn to the positive end 136 of filter capacitor 135 and the positive side 141 of the load 140.

A transistor drive circuit 145 is connected to the base 108 of the IGBT switching device 105. The negative end 112 of the DC source voltage 110, anode 127 of diode 125, the negative end 137, of capacitor 135, and the negative side 142, of the load 140, are connected to ground 150.

FIGS. 2A-2F illustrate the time during which various power losses occur and the magnitude of the losses in regard to the switching circuit 100 of FIG. 1 in accordance with the prior art.

VI Turn-Off Loss

FIG. 2A illustrates VI turn-off loss. When switching off the IGBT switching device 100 (switch), the currents and current paths do not change (assuming there is a large filter inductor) until the voltage across the switch is higher than the DC source voltage 110, at which time the current will start to fall. As shown in FIG. 2A the current through the switch, represented by solid line 205, is constant from time t0 to time t1 during which the voltage across the switch, represented by dashed line 210 rises to the level of the DC source voltage 110. When the voltage across the switch reaches the level of the DC source voltage 110 (e.g., at time t.sub.1), the current will fall until it reaches zero (at time t.sub.2). Note that FIG. 2A assumes no tail current (described below) in the switch.

When the switch is turned off, the current commutates to the diode 125 as follows. The current decays at a rate determined by the size of the inductors 115 and 120 and the voltage level above the DC source voltage 110. That is, when the voltage across switch is higher than DC source voltage 110, the amount of voltage over and above the DC source voltage 110 will divide between inductors 115 and 120 with the end 117 of inductor 115 and the end 121 of inductor 120 being positive. The voltage will divide in the ratio of the size of inductors 115 and 120 such that -di/dt of inductor 115 will be equal to the +di/dt of inductor 120. This process will continue until the current reaches zero in the switch. When the current reaches zero the voltage across the switch will drop to approximately the voltage level of the DC source voltage 110.

As shown in FIG. 2A, the VI turn-off power loss is represented by hatched area 215 and occurs during the period in which the voltage across the switch begins to rise and before the current falls to zero (e.g., from time t0 to time t2). The VI turn-off loss is typically the highest of the switching losses and can be substantial especially for circuits employing HSM. For example, for a typical system in which the current is 1,000 amps (A) and the voltage is 600 volts (V), the power loss at the peak power point (e.g., time t.sub.1) is 600 kilowatts (kW) and the average power loss is approximately 300 kW over the time t.sub.0 to t.sub.2. This time may typically approach 10% of the switching period resulting in a VI turn-off loss of 30 kW.

Tail Current Loss

While the VI turn-off loss applies to circuits implementing a bi-polar device as well as to circuits implementing a field effect transistor (FET), an additional turn-off loss, particular to most circuits implementing a bi-polar switching device is the tail current turn-off loss (tail current loss).

FIG. 2B illustrates tail current loss. As shown in FIG. 2B, the voltage represented by dashed line 225 is the same as that shown in FIG. 2A and the current represented by solid line 220 falls in a manner similar to that shown in FIG. 2A during the period from time t.sub.1 to time t.sub.2. The size of inductors 115 and 120, and the voltage level across the switch above the DC source voltage 110 determines the rate at which the current decays until time t.sub.2. For most bi-polar device, a point (e.g., time t.sub.2) is reached at which the switching device itself determines the current decay rate and the current decays at a slower rate thereby increasing the power loss. The power loss between time t.sub.2 and time t.sub.3 is the tail current loss. The cause and extent of tail current losses are complex, but are generally due to charges stored in the device due to minority carrier injection that occurs with current conduction through most bipolar devices and determined by the voltage and current turn-off conditions and the switching time. For example, for a switching device implementing an IGBT, a lower voltage rating of the switching device for a given voltage at turn-off, results in a lower tail current because there will be fewer stored charges in the device in its saturated, on-state, condition.

The tail current losses are typically much lower than the VI turn-off losses from time t.sub.0-time t.sub.2. If the VI turn-off loss is reduced and the circuit is switched at substantially higher frequencies, the tail current losses at such higher switching frequencies may be substantially greater than typical VI turn-off losses at a lower frequency. It is for this reason that the tail current losses are considered a significant disadvantage of typical prior art schemes.

VI Turn-On Loss

FIG. 2C illustrates VI turn-on loss. When the switch is turned on, the current across the switch starts to rise as soon as the voltage across the switch begins to fall. As shown in FIG. 2C the current through the switch, represented by solid line 235 does not begin to rise until the voltage, represented by dashed line 240, begins to fall (i.e. at time t.sub.1). Therefore from time t.sub.0 to time t.sub.1 there is no VI turn-on loss. The VI turn-on power loss is represented by hatched area 245 and occurs during the period in which the current across the switch begins to rise and before the voltage falls to zero (e.g., from time t.sub.1 to time t.sub.2). The VI turn-on loss depends on the rate at which the voltage falls and the rate at which the current rises. If the voltage falls during the same period in which the current rises, then the VI turn-on loss would be similar to that shown in FIG. 2A (though not as great because upon turning off the switch the current doesn't begin to fall until after the voltage has risen above the DC source voltage). If the time required for the current to rise is greater than the time required for the voltage to fall, then the VI turn-on loss is reduced proportionally.

When turning the switch on, if the voltage drops to substantially 0 V before the current starts to rise, then the switch will have no (or negligible) VI turn-on loss. In some soft switching topologies (one or more switching losses not present), discussed more fully below, this condition is the result of the voltage and current timing effects of the circuit topology (e.g., the inductors and capacitors added to the circuit to attain soft switching). This is illustrated in FIG. 2E in which the voltage represented as dashed line 270 falls to near 0 volts at a time (e.g., time t.sub.1) prior to the time (e.g., time t2) at which the current represented as solid line 265 begins to rise.

Conductivity Modulation Loss

While the VI turn-on loss applies to circuits implementing a bi-polar device as well as to circuits implementing a field effect transistor (FET), an additional turn-on loss, particular to circuits implementing a bi-polar switching device is the conductivity modulation loss (CM loss), also referred to as conduction modulation loss.

FIG. 2D illustrates the CM loss for a switch implementing a bi-polar device. As shown in FIG. 2D, the current through the switch represented by solid line 250 is the same as that shown in FIG. 2C and the voltage across the switch represented by dashed line 255 falls in a manner similar to that shown in FIG. 2C during the period from time t.sub.1 to time t.sub.2. From time t.sub.2 to time t.sub.3 conductivity modulation occurs increasing the turn-on loss. This period is referred to as conductivity modulation time.

In a bipolar device, the n-region (assuming this is the region that is predominantly responsible for blocking voltage in the off state) of the device, just after starting to conduct current, has a higher effective resistance than it has after the current has been flowing for some time. As the current flows the effective resistance of the n-region goes down since minority carriers injected into the n-region (by initial current flow) reduce the n-region resistivity and thus modulate the conductivity. After several microseconds (starting at time t.sub.2 in FIG. 2D), the forward voltage drop of the bipolar device will reach its DC forward drop voltage (at time t.sub.3 in FIG. 2D) for the current flowing. For example, the forward drop of a bi-polar transistor device at full load (e.g., 100 A) may be 40 V. After the current has been flowing for some time (e.g., 10 microseconds) the forward load may drop to 2 V. The resistance has changed from 0.4 ohms to 0.02 ohms (e.g., the resistance of the device has been modulated as the device conducts current).

The turn-on losses of a switch implementing a bi-polar device are represented by hatched area 260 and occur during the period in which the current through the switch begins to rise and before the voltage falls to zero (e.g., from time t.sub.1 to time t.sub.3). The CM losses are those losses between time t.sub.2 and time t.sub.3.

The CM losses are typically much lower than the VI turn-on losses. For example, the CM losses are typically about 20% of the VI turn-on losses. If the VI turn-on loss is reduced and the circuit is switched at substantially higher frequencies, the CM losses at such higher switching frequencies may be substantially greater than typical VI turn-on losses at lower frequencies. It is for this reason that CM losses, like tail current losses described above, are considered a significant disadvantage of typical prior art schemes.

Circuits implementing a bi-polar device and having topologies that result in the voltage dropping to near 0 volts before the current starts to rise will still have CM losses. Such CM losses are illustrated in FIG. 2F in which the voltage represented as dashed line 285 is at or near 0 volts until the current represented as solid line 280 begins to rise at time t.sub.1. The voltage rises as the current rises from time t.sub.1 to time t.sub.2 due to conduction modulation. The voltage then falls to a low voltage at a time t.sub.3. The conductivity modulation losses represented by hatched area 290 are incurred from time t.sub.1 to time t.sub.3.

Capacitive Loss

All switching devices have a capacitance across their power terminals. The capacitance is from the collector to emitter in IGBTs and bi-polar transistors. When the switching device turns on, the capacitance is discharged into the switching device. The energy stored in the capacitor is absorbed in the switching device itself and becomes part of the turn-on switching losses. Typically the energy absorbed is small, even at high frequencies. Soft switching topologies exist that naturally discharge the capacitance before the switching device is turned on with no added circuitry.

Free Wheeling Diode Switching Loss

The switching losses described above did not take into account the sweep out current of the free wheeling diode 125 of FIG. 1 during turn-on. That is, when the switch is off, current is freewheeling through a filter inductor. When the switch is turned on, the current of the diode is reversed until the diode starts to block. At this point, the voltage across the diode increases dramatically resulting in substantial losses in the diode with a corresponding current over shoot in the current in the switching device 105, and significantly more switching loss in the switching device 105, which is not illustrated in FIG. 2C.

Soft-Switching Topologies

There are soft switching topologies that do not have diode turn-on switching loss (e.g., the diode is blocking voltage prior to turn on). For HSM, especially under high voltage conditions, the sweep out current is very high and increases the losses during turn-on to several times that shown in the FIGS. 2A and 2B.

Some attempts have been made to make inverter circuits using so-called "soft switching" mode (SSM) in which the voltage is switched when current through the device is zero, or where the current is switched when voltage across the device is zero. For circuits operating in SSM, one or more of the major switching losses is not present. Soft switching is achieved by using inductors and capacitors to delay current and/or voltage changes. This can result in increased costs and generate undesirable circuit conditions and fault requirements. Moreover, SSM applications reduce either the VI turn-on switching losses or the VI turn-off switching losses, but normally do not address both losses.

Other attempts to address switching losses through varied circuit topologies or modulation schemes have been made but these have not addressed all switching losses in one circuit. For example, some schemes have included loss-reduced snubbers, filters, or additional power devices to assist and/or share current or voltage during switching to reduce VI turn-off losses in the main conduction device, but without addressing VI turn-on losses due to the free wheeling diodes. For example, for low power applications using a metal-oxide semiconductor (MOS) device to control switching in voltage source inverters may employ fast switching and snubbering to reduce VI turn-off losses, but VI turn-on losses and free wheel diode losses remain. CM losses, which are a function of device design, may typically be reduced by modifying the device design, however, this may result in increased switching losses.

Other efforts have been made to address VI turn-on loss, but without addressing VI turn-off loss, diode loss, or other losses such as CM losses and tail current losses incurred with bipolar devices typically employed in high power applications. For such devices, switching losses are typically the determining factor in power handling limitations and in frequency limitations.

SUMMARY OF THE DESCRIPTION

An inverter switching circuit for reducing switching losses. The circuit has a switching device and a voltage source electrically coupled to the switching device, the voltage source providing a normal operational voltage for the inverter switching circuit. The switching device also includes a switching voltage reduction mechanism for substantially reducing the voltage across the switching device, relative to the normal operational voltage, during a turn-off time of the switching device, the switching voltage reduction mechanism maintaining a substantially reduced voltage across the switching device during at least a portion of a tail current loss time of the switching device. The switching voltage reduction mechanism is also used during the turn-on of a switching device to reduce the turn-on switching losses according one embodiment.

This application addresses all the significant switching losses in each embodiment. This is done with added circuitry and sometimes in conjunction with a soft switching topology. It also addresses a modulation technique where the switching losses are significantly (e.g., approximately 50%) reduced with logic changes only in multi-switch PWM inverters. This is done by using a modulation technique that does not turn off which ever switch is carrying the most current during each PWM cycle.

Other features of the present invention will be apparent from the accompanying drawings and from the detailed description which follows.

DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar elements.

FIG. 1 is a schematic diagram illustrating a conventional switching circuit.

FIGS. 2A-2F are diagrams illustrating the time during which power loss occurs and the magnitude of the loss of a typical switching circuit.

FIGS. 3 and 3A are flow diagrams illustrating a process for reducing multiple losses of a switching device in accordance with certain embodiments of the invention.

FIG. 4 is a schematic diagram illustrating an exemplary circuit that may be used to reduce power losses of a switching device, according to one embodiment.

FIG. 5 is a schematic diagram illustrating an exemplary circuit that may be used to reduce power losses of a switching device according to another embodiment.

FIG. 6 is a schematic diagram illustrating an exemplary circuit for reducing power losses of a switching device according to another embodiment.

FIGS. 7A-7C are schematic diagrams illustrating exemplary circuits, which may be used to reduce power loss according to certain embodiments.

FIG. 8 is a schematic diagram illustrating a switching circuit for reducing power losses of a switching power converter according to one embodiment.

FIGS. 8A-8I are schematic diagrams illustrating various configurations of circuits for reducing power losses of a switching power converter according to certain embodiments.

FIGS. 9A-9C are schematic diagrams illustrating various configurations of circuits for reducing power losses of a switching power converter according to other embodiments.

FIGS. 10, 10A, and 10B are diagrams illustrating a typical soft-switching topology.

FIGS. 10C-10G are diagrams illustrating an exemplary soft-switching topology according to one embodiment of the invention.

FIGS. 11 and 11A are diagrams illustrating an exemplary modulation scheme according to one embodiment of the invention.

FIGS. 12 and 12A-12C are diagrams illustrating an exemplary modulation scheme according to another embodiment of the invention.

FIG. 13 is a schematic diagram illustrating an exemplary lossless filter.

DETAILED DESCRIPTION

Power losses reduction in switching power converters is described herein. Embodiments of the invention provide methods and apparatuses for substantially concurrently eliminating or substantially reducing two or more switching losses in an inverter switching circuit. Embodiments of the invention substantially concurrently reduce multiple types of switching losses under HSM and SSM for active switching devices and diodes.

Embodiments of the invention provide substantial reduction or elimination of switching losses, thereby improving efficiency, enabling higher power ratings for a given size of equipment, reducing the size of required heat sinking to manage the losses, and also enabling much higher switching frequencies to be used.

Embodiments of the invention significantly reduce all or most of the sources of switching losses substantially concurrently and therefore provide virtually lossless switching with existing device types. Moreover, with such reduced-loss switching, greater reduction in system losses and hardware cost can be obtained by optimizing the switching device DC forward drop design without consideration of the switching loss tradeoffs as required by prior art schemes.

In one embodiment of the invention, a high-speed switching device (e.g., a FET) is implemented in parallel with the bi-polar switching device of the switching circuit to substantially reduce the VI turn-off loss. In one embodiment, the FET is left turned on long enough to substantially reduce the tail current loss.

In one embodiment of the invention, a saturable reactor circuit is implemented in series with the bi-polar switching device to substantially reduce VI turn-on loss. Additionally, for an alternative embodiment, a resistor is implemented in parallel with the saturable reactor to substantially reduce CM loss.

In one embodiment of the invention, switching device turn-on losses, switching device turn-off losses and diode losses are addressed substantially concurrently in order to provide reduced-loss switching without incurring additional fault conditions (e.g., actually significantly reducing the fault conditions of conventional circuits). In one embodiment, turn-on losses may be reduced by delaying the current through the device until a predetermined time period, also referred to as a pre-conditioning period, has passed in which the device is somehow saturated. As a result, the device can conduct current without current rise loss and/or without CM loss. In one embodiment, turn-off losses may be reduced by deferring application of a voltage until the device has been prepared to block a voltage without incurring loss, for example, by removing stored charges and/or recovering the device before full voltage is applied. In one embodiment, diode losses may be reduced by switching the diode during the pre-conditioning period of switching device prior to turning on. In another embodiment, the diode switching losses may be reduced by using a topology in which the diode is supporting a voltage before the voltage across the diode goes to a relatively high value (e.g., there is little or no reverse sweep out current in the diode).

In the following description, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known circuits, structures and techniques have not been shown in detail in order not to obscure the understanding of this description.

Reference throughout the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearance of the phrases "in one embodiment" or "in an embodiment" in various places throughout the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Moreover, inventive aspects lie in less than all features of a single disclosed embodiment. Thus, the claims following the Detailed Description are hereby expressly incorporated into this Detailed Description, with each claim standing on its own as a separate embodiment of this invention.

Processes

FIG. 3 illustrates a process by which multiple losses of a switching device are substantially reduced in accordance with one embodiment of the invention. Process 300, shown in FIG. 3, includes operation 305 in which the voltage across a switch is substantially reduced during the switch turn-off time. For example, the voltage across the switch may be reduced to one-tenth of the normal switching voltage. The voltage across the switch is kept low during the VI turn-off loss time. That is, the time in which the current through the switch falls to approximately zero ampere (e.g., until time t2 of FIG. 2A). Because the voltage across the switch is substantially reduced, the VI turn-off loss is likewise substantially reduced.

At operation 310, for circuits implementing a bi-polar switching device, the substantially reduced voltage across the switch is maintained throughout the tail current time (e.g., until time t3 of FIG. 2B). Maintaining the substantially reduced voltage across the switch provides substantially reduced tail current losses in addition to substantially reduced VI turn-off losses.

In accordance with various embodiments of the invention, various circuit topologies may be implemented which substantially reduce the voltage across the switch during the VI turn-off loss time and/or tail current loss time. Several such circuit topologies will be discussed in greater details below in accordance with various described embodiments. It will be apparent to those skilled in the art that many more such circuit topologies are possible.

At operation 315 the voltage across the switch is allowed to return to normal switching voltage (e.g., approximately the source voltage 110 of FIG. 1). At operation 320 the voltage across the switch is substantially reduced prior to the switch turn-on time. That is, prior to the time at which the current begins to rise (time t1 of FIG. 2C).

As noted above, there are SSM topologies that provide a substantially reduced voltage across the switch prior to the current beginning to rise. However, embodiments of the invention substantially reduce voltage across the switch prior to the switch turn-on time using HSM topologies, discussed below, that do not have the noted disadvantages of SSM topologies. Because the voltage across the switch is substantially reduced, the VI turn-on loss is likewise substantially reduced.

The capacitive loss is also substantially reduced. The capacitive losses, the energy absorbed in the device when the switch is turned on, are approximated by equation 1. Power loss=1/2*C*V.sup.2*f (1) Where C is the effective capacitance of the across the switch, V is the voltage across the switch, and f is the switching frequency. Therefore, a substantial reduction in the voltage across the device will result in an even more substantial reduction in capacitive loss.

Moreover, the diode switching loss is substantially reduced as well. That is, substantially reducing the voltage across the switch at turn-on time prevents the dramatic increase in voltage across the diode that results in freewheeling diode switching loss. Therefore, with a reduced voltage across the device at switch on time, the loss in switching device 22, due to the sweep out of the diode, is very small relative to when VI turn-on loss and CM loss are present at full voltage. This applies to systems designed to run with lower losses at a given frequency (e.g., 3 KHz) or, alternatively, designed to run at much higher frequencies (e.g., 30 KHz to 300 KHz).

Thus, embodiments of the invention substantially reduce the voltage across the switch at specific times and for specific durations thereby substantially and concurrently reducing some or all of the VI turn-off loss, VI turn-on loss, tail current loss, capacitive loss, and freewheeling diode switching loss. The amount the losses are reduced is proportional to the reduction in voltage. For purposes of this discussion a substantial reduction in voltage means a reduction to 50% or less of the normal switching of the device.

Conductivity Modulation Loss

Process 300, described above in reference to FIG. 3 provides substantially reduced VI turn-off loss, VI turn-on loss, tail current loss, capacitive loss, and freewheeling diode switching loss, but does not address CM loss. That is, because CM loss is a function of the current and not the voltage across the switch, substantially reducing the voltage at turn-off time and turn-on time will not address CM loss. CM loss is typically approximately 20% of the VI turn-on loss, while the VI turn-on loss is approximately 50% of the VI turn-off loss. Therefore CM loss is not significant compared to the aggregate of the other losses addressed through process 300. However, once the VI turn-off loss, VI turn-on loss, tail current loss, capacitive loss, and/or freewheeling diode switching loss have been addressed, it becomes practical to switch at higher frequencies. At higher frequencies, the CM loss becomes substantial and cannot be ignored in many cases.

Embodiments of the invention, therefore, address the CM loss by substantially reducing the current during conductivity modulation time (e.g., time t1 through time t3 of FIG. 2D). The full switching current is not required to lower the effective resistance of the switch. Therefore, in accordance with one embodiment of the invention, a substantially reduced current (e.g., 10% of the normal switching current) is employed prior to the switch turn-on to lower the effective resistance. The reduced current is maintained until conductivity modulation is effected. The substantially reduced current results in proportionally reduced CM loss.

FIG. 3A illustrates a process that includes substantially reducing the current in the switch during switch turn-on to reduce CM loss in accordance with one embodiment of the invention. Process 300A, shown in FIG. 3A, includes operation 305-320 as described above in reference to process 300 of FIG. 3. Process 300A also includes operation 325 in which the current through the device is substantially reduced prior to the switch turn-on. The current is reduced to a level that is sufficient to effect conductivity modulation and is maintained until conductivity modulation is effected.

Exemplary Circuit Topologies

In one embodiment of the invention, the VI turn-off losses and/or the tail current losses are substantially reduced by holding the voltage across the switching device relatively low (e.g., compared to the switching voltage) during the VI turn-off loss time and the tail current loss time of the switching device.

FIG. 4 is a schematic diagram illustrating an exemplary circuit that may be used to reduce power losses of a switching device, according to one embodiment. In this circuit example, a switching circuit includes a high-speed switching device in parallel with a bi-polar switching device. Referring to FIG. 4, circuit 400 operates in a similar manner to circuit 100 described above in reference to FIG. 1, and the same reference numbers are used to identify the same circuit components. As shown in FIG. 4, according to one embodiment, a FET 455 is implemented in parallel with the IGBT switching device (IGBT) 105 with the FET source 456 connected to the IGBT emitter 107 and the FET drain 457 connected to the IGBT collector 106. The IGBT is exemplary and could be replaced by any bi-polar device (e.g., GTO, IGCT, bi-polar transistor, etc.) in alternative embodiments. Likewise the FET 455 may be implemented as any fast switching device in alternative embodiments.

In general, the FET 455 switches much faster than IGBT 105 and typically, a FET may switch 10-100 times faster than an IGBT. Note that the voltage across the FET is relatively low before it turns on. The faster switching and the relatively low voltage result in reduced VI turn-off switching loss. For example, the VI turn-off loss of the FET may only be 0.5%-5% of the VI turn-off loss for an IGBT. Therefore, sometime (e.g., a predetermined period of time) prior to a desired turn-off time, in one embodiment, the IGBT 105 is turned off and the FET 455 is turned on. The current goes through the FET 455 instead of the IGBT 105 so that there is no or less VI turn-off loss associated with the IGBT 105, only a greatly reduced VI turn-off loss associated with the FET 455, which is much less than those associated with the IGBT 105.

Moreover, a FET, inherently, has no or less tail current loss, so if the FET is left turned on for a sufficient period, according to one embodiment, the tail current loss associated with the IGBT will be greatly reduced or eliminated. The FET 455 may be turned on and/or off by a control signal received at the gate of the FET 455. The gate of the FET 455 may be coupled to a separate drive circuit or the same drive circuit 145, with or without intermediate components in between.

To reduce VI turn-off loss and tail current loss, the IGBT 105 and the FET 455 are operated in the following manner. During a predetermined period of time prior to a desired switching circuit turn-off time, the FET 455 is turned on and concurrently the IGBT 105 is turned off. For a typical IGBT, this time period may be approximately 3-6 microseconds. When the FET 455 is turned on, the voltage across the FET 455 is relatively low and has a relatively low VI turn-on loss with virtually no CM loss.

The FET 455 is kept on for all or most of the time it takes the IGBT 105 to turn off, where off is defined as when the IGBT 105 having negligible or no tail current when the voltage appears on the IGBT 105. This maintains the voltage across the IGBT 105 at a low value during the VI turn-off loss time and tail current loss time. Therefore the VI turn-off losses of the IGBT 105 are substantially reduced as compared to conventional schemes (e.g., circuit 100).

When the IGBT 105 has regained its forward blocking ability and the tail current time has passed, the FET 455 is turned off. The remainder of the turn-off process is the same as that of circuit 100 as described above in reference to FIG. 1. The current commutates to the diode 125 in the following way. When the voltage across the IGBT 105 is higher than the DC source voltage 110, the amount of voltage higher than DC source voltage 110 will divide proportionally between inductors 115 and 120. This process will continue until the current reaches 0 A in FET 455. When the current reaches 0 A, the voltage across FET 455 will drop to approximately the level of the DC source voltage 110, thus substantially reducing the turn-off switching losses in the IGBT 105.

FIG. 5 is a schematic diagram illustrating an exemplary circuit that may be used to reduce power losses of a switching device according to another embodiment. In this example, the switching circuit includes a saturable reactor circuit in series with a bi-polar switching device. Note that circuit 500 operates in a similar manner to circuit 400 described above in reference to FIG. 4, and the same reference numbers are used to identify the same circuit components. Referring to FIG. 5, according to one embodiment, a saturable reactor 560 is implemented in series with the IGBT 105. The saturable reactor 560, which may be, for example, a near "square loop" saturable reactor, is constructed so as to have a saturation time sufficient to hold off the source voltage 110 until the voltage across switching device falls to approximately 0 V after being turned on, for example, as shown in FIG. 2E.

According to one embodiment, when IGBT 105 is turned on, the voltage across IGBT 105 falls, but only a minimal current (approximately 0.5 A-5 A) flows due to the high impedance of the saturable reactor 560. After the saturable reactor 560 is saturated, the current rises to normal switching current. Therefore, the saturable reactor 560 is selected such that its saturation time is sufficient to allow the voltage across the switching device (e.g., IGBT 105) to fall to near zero before the current begins to rise, thereby substantially reducing VI turn-on loss.

In use, the saturable reactor 560 time starts prior to the desired turn-on time of the switching device if the saturable reactor were not used. For example, if the saturation time of the saturable reactor is 3 microseconds, then the switching device is turned on 3 microseconds prior to the desired turn-on time of the switching circuit. During this time, the voltage across the switch falls to approximately 0 V with minimal current (e.g., only the coercive current of the saturable reactor).

Reset circuit 561 is used to reset the saturable reactor 560 by applying a positive voltage on end 562 of the saturable reactor 560 for a period sufficient to saturate the saturable reactor 560 in the opposite direction that it will be when full load current is flowing through IGBT 105. The resetting is achieved when IGBT 105 and FET 455 are off.

FIG. 6 is a schematic diagram illustrating an exemplary circuit for reducing power losses of a switching device according to another embodiment. In this example, a switching circuit includes a saturable reactor circuit and parallel resistor in series with a bi-polar switching device in accordance with one embodiment of the invention. Circuit 600, shown in FIG. 6, operates in a similar manner to circuit 500 described above in reference to FIG. 5, and the same reference numbers are used to identify the same circuit components.

As shown in FIG. 6, according to one embodiment, a resistor 665 is implemented in parallel with the saturable reactor circuit 560 and in series with the IGBT 105. The resistor 665 allows a current that is substantially lower than the full switching current, but sufficient to effect conductivity modulation. That is, the coercive current of the saturable reactor 560 which is typically approximately 1 A is not sufficient to lower the resistance through the switch. The resistor 665 allows a sufficient current to flow in order to effect conductivity modulation, that is, the current is reduced to a level that is sufficient to effect conductivity modulation and is maintained until conductivity modulation is effected. Therefore, when the saturable reactor 560 saturates, and the current rises to full switching current, the conductivity modulation has already occurred. In certain embodiments, resistor 665 may not be required when the switching device 107 is a non-bipolar device, since the non-bipolar device such as a FET has relatively less or no CM loss.

The value of the resistor 665 may be determined based on various considerations including the extent of CM loss reduction, the time required to overcome the CM effect, and the size and cost of the saturable reactor. For example, a higher current yields greater CM losses, but would reduce the cost of the saturable reactor because the saturable reactor time would be reduced.

Thus, circuits 400, 500, and/or 600 described above, concurrently and substantially, reduce or eliminate multiple switching losses in accordance with various embodiments of the invention. The inventive concepts of various embodiments enable significant reduction in the size and cost of power systems as well as significantly decreasing the losses in high power systems. The reduced losses realized by such circuits save power, reduce operating costs, and allow switching at higher frequencies and/or running at higher power as discussed more fully below.

Circuit 600 demonstrates one embodiment of an HSM circuit in which all of the major turn-on losses and turn-off losses are substantially reduced. For illustrative purposes, the operation of circuit 600 is provided. For initial conditions in which that the switching device is on and conducting current and the saturable reactor is saturated, the description of the operation of circuit 600 is as follows.

A short time (e.g., 0.3 to 6 microseconds) before the switching circuit is to be turned off, the FET 455 (or other fast switching device) is turned on and the IGBT 105 is turned off.

The time is a function of the voltage rating and manufacturing process of the IGBT (or other bipolar device) being used. This time will depend on many circuit parameters, but in general, the FET 455 is kept on for a long enough time such that when it is turned off the IGBT 105 will be fully off and will not have any tail current when the voltage rises across the parallel combination of the IGBT 105 and the FET 455. In this way the VI turn-off loss and the tail current loss are substantially reduced because the switching losses in a FET are much lower than that of an IGBT (or other bi-polar device) and the FET has no tail current.

After the turn-off of the switching circuit is completed, the reset circuit 561 is turned on to reset the saturable reactor 560. At any time after the saturable reactor 560 has been reset, the IGBT 105 may be turned back on. When the transistor drive circuit 145 turns on (e.g., logically high), the voltage across the IGBT 105 will drop to a low voltage in a very short time. The voltage across the saturable reactor 560 will be slightly less than the source voltage 110. The current in the IGBT 105 will be slightly less than the source voltage 110 divided by the resistor 665. The current will not change until the saturable reactor 560 is saturated, at which time the current will quickly rise to the value that is flowing in filter inductor 130. Note that the switching losses in the diode 125 are relatively high thus limiting the maximum switching frequency of such circuits.

The saturating time of the saturable reactor 560 is set so that the current through the IGBT 105 will reduce the resistance of the n-region to near its saturated value with significantly less CM loss than there would be if the current rose to full load current as soon as the IGBT 105 is turned on. In this way the CM loss of the IGBT 105 is significantly reduced with the VI turn-on losses reduced to very near zero. This completes one cycle of operation of circuit 600.

As discussed above, a FET may be used to substantially reduce the voltage across a switch to effect a reduction in VI turn-off loss and tail current loss. The use of the FET is such a manner is not without disadvantages. For example, commercially available FETs are relatively expensive and their implementation for high power applications is not practical. As noted, embodiments of the invention may substitute any fast switching device for the FET. For one alternative embodiment, in which the switching device is a bi-polar transistor, if a fast rise time/high turn-off current is used, according to one embodiment, the FET may be replaced with a small capacitor as shown in FIGS. 7A-7B for example. Such an approach may have much higher losses, but eliminates the requirement of expensive FETs.

FIG. 7A is a schematic diagram illustrating an exemplary circuit which may be used to reduce power loss according to another embodiment. In this example, a switching circuit includes a capacitor in parallel with a switching device in accordance with one embodiment of the invention. Circuit 700, shown in FIG. 7A according to one embodiment, operates in a similar manner to circuit 600 described above in reference to FIG. 6, and the same reference numbers are used to identify the same circuit components.

As shown in FIG. 7A, in place of FET 455, circuit 700 implements a capacitor 780. Capacitor 780 is near 0 V at switch turn-off. The current in the IGBT 105 is then transferred to the capacitor 780. The capacitor voltage rises over a predetermined period of time (e.g., the capacitor charge time). The capacitor value can be selected to provide a capacitor charge time that extends beyond some or all of the tail current loss time, thus reducing or eliminating VI turn-off loss and tail current loss. At turn-off, then, current flows into the capacitor 780. Therefore, because the current through the switching device 105 has been bypassed immediately through the capacitor 780, the VI turn-off losses are substantially reduced. If the charge time of capacitor 780 is of sufficient duration, then the tail current loss is substantially reduced as well.

According to one embodiment, a lossless filter may be used instead of capacitor 780. FIG. 7B is a schematic diagram illustrating an exemplary circuit which may be used to reduce power loss according to another embodiment. In this example, a switching circuit includes a lossless filter 180A in parallel with a switching devic





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